Optimal solution in producing 32-nm CMOS technology transistor with desired leakage current

Abstract

The objective of this paper is to optimize the process parameters of 32-nm CMOS process to get minimum leakage current. Four process parameters were chosen, namely: (i) source-drain implantation, (ii) source-drain compensation implantation, (iii) halo implantation time, and (iv) silicide annealing time. The Taguchi method technique was used to design the experiment. Two noise factors were used that consist of four measurements for each row of experiment in the L9 array, thus leading to a set of experiments consisting of 36 runs. The simulator of ATHENA and ATLAS were used for MOSFET fabrication process and electrical characterization, respectively. The results clearly show that the compensation implantation (46%) has the most dominant impact on the resulting leakage current in NMOS device, whereas source-drain (S/D) implantation was the second ranking factor (35%). The percent effects on signal-to-noise ratio (SNR) of silicide annealing temperature and halo implantation are much lower being 12% and 7%, respectively. For the PMOS device, halo implantation was defined as an adjustment factor because of its minimal effect on SNR and highest on the means (43%). Halo implantation doping as the optimum solution for fabricating the 32-nm NMOS transistor is 2.38×10¹³atom/cm³. As conclusion, this experiment proves that the Taguchi analysis can be effectively used in finding the optimum solution in producing 32-nm CMOS transistor with acceptable leakage current, well within International Technology Roadmap for Semiconductor (ITRS) prediction.