Fabrication and characterization of a 0.14 μm CMOS device using ATHENA and ATLAS simulators

Abstract

A 0.14 µm CMOS transistor with two levels of interconnection was designed and simulated to investigate its functionality and characteristics. ATHENA and ATLAS simulators were used to simulate the fabrication process and to validate the electrical characteristics, respectively. A scaling factor of 0.93 was applied to a 0.13 µm CMOS. The parameters being scaled are the effective channel length, the density of ion implantation for threshold voltage (Vth) adjustment, and the gate oxide thickness. In order to minimize high field effects, the following additional techniques were implemented: shallow trench isolation, sidewall spacer deposition, silicide formation, lightly doped drain implantation, and retrograde well implantation. The results show that drain current (ID) increases as the levels of interconnection increases. The important parameters for NMOS and PMOS were measured. For NMOS, the gate length (Lg) is 0.133 µm, Vth is 0.343138 V, and the gate oxide thickness (Tox) is 3.46138 nm. For PMOS, Lg is 0.133 µm, Vth is −0.378108 V, and Tox is 3.46167 nm. These parameters were validated and the device was proven to be operational.