The effect of doping methods on electrical properties and micromorphology of polysilicon gate electrode in submicron CMOS devices

Abstract

Two doping methods for introducing phosphorus atoms into polysilicon to form a gate electrode for 0.5 mm CMOS were investigated. These methods were ion implantation and the ”in-situ” one (it is also known as thermal diffusion). For the in-situ method, the concentration of 1.8.10²⁰cm-³ for Si₂H₆ and phosphane (PH3) were used, in the course of ion implantation applying two different doses: 2.0.10¹⁶ and 3.10¹⁶cm-² at 40 keV. The micromorphology of the polysilicon surface was studied using the atomic force microscopy (AFM). The polysilicon thickness obtained via the in-situ method ranged between 12.35 and 26.08 nm, with an average value thickness of 18.0 nm, and its sheet resistance value was 21±1 ohm/square. As for the ion implantation method, at the lower doses the thickness ranged at about 12.00 upto 46.0 nm with an average value of 24.0 nm, and its sheet resistance values were of 36±13 and 45±21 ohm/square, respectively. At the higher doses, the thickness varied from 12.16 to 47.84 nm with an average meaning 23.96 nm, and its sheet resistance value was between 25 to 40 ohm/square. Therefore, polysilicon doped by the in-situ method has smoother and thinner surface and possesses better electrical properties.