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dc.contributor.author |
Chapyzhenka, A. |
|
dc.contributor.author |
Ragozin, D. |
|
dc.contributor.author |
Umnov, A. |
|
dc.date.accessioned |
2008-07-28T18:54:51Z |
|
dc.date.available |
2008-07-28T18:54:51Z |
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dc.date.issued |
2005 |
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dc.identifier.citation |
Low-power architecture for CIL-code hardware processor/ A. V. Chapyzhenka, D.V. Ragozin, A.L. Umnov // Проблеми програмування. — 2005. — N 4. — С. 20-38. — Бібліогр.: 16 назв. — англ. |
en_US |
dc.identifier.issn |
1727-4907 |
|
dc.identifier.uri |
http://dspace.nbuv.gov.ua/handle/123456789/1372 |
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dc.description.abstract |
In the article the authors present the architecture of a hardware CIL processor, which is capable to execute CIL instructions as native code. The CIL hardware engine is implemented on the top of the low-power DSP architecture, and the CIL processor has two execution cores: DSP and CIL. Such solution allows to execute both CIL and DSP instruction sets as native instructions sets and gain performance in common multimedia tasks. Therefore, the DSP-based CIL processor may be targeted for multimedia digital home and even embedded applications. The research was sponsored by RFP 2 Microsoft Corp. grant. |
en_US |
dc.language.iso |
en |
en_US |
dc.publisher |
Інститут програмних систем НАН України |
en_US |
dc.subject |
Інструментальні засоби і середовища програмування |
en_US |
dc.title |
Low-power architecture for CIL-code hardware processor |
en_US |
dc.type |
Article |
en_US |
dc.status |
published earlier |
en_US |
dc.identifier.udc |
004.273 |
|
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