Interface model of low temperature plasticity in high uniaxially strained monocrystalline semiconductors

Abstract

The manifestation of the low temperature plasticity (LTP) in highly uniaxially strained Ge and Si single crystals was deduced from analysis of the both tensoeffect measurements data and defect-selective etching patterns of specimens. An appearance of additional tensoeffect mechanisms after the LTP display we attribute to the generation of electrical active defects of crystalline structure when the applied stress exceed some critical one. We found that under LTP conditions the generated dislocation pile-ups are directly concentrated in the phase-boundary field of some structural imperfections of crystalline lattice. The interface model of LTP phenomenon in monocrystalline semiconductors was proposed for acceptable explanation of the dislocation generation in the initially dislocation-free crystals.